Salient Features of Languages
Some of the most widely compared and contrasted features of Verilog and VHDL are:
1. Concurrency : A common characteristic of both these hardware description languages is that unlike software programming languages like C, Java and C++ etc., both these languages are concurrent in their behavior and program execution, as these languages are meant to design and simulate hardware.
2. Predefined Constructs: As compared with VHDL, Verilog HDL has more predefined operators, predefined gates and predefined resolution functions. Verilog also includes don't care notation.
3. Lower Level Modeling Capability: Verilog is better suited to modeling devices at lower level (i.e., Gate Level and Switch Level) than VHDL. This is why Verilog is deemed more efficient and appropriate for IC designing.
4. Modeling Primitive Capability: As compared with VHDL, Verilog includes convenient truth table syntax to model primitives. However, the VITAL packages in VHDL provide this feature.
5. High Level Modeling Capability: As compared with Verilog, VHDL includes more constructs (abstract data types and packages etc.) for high level modeling. This is why VHDL is considered appropriate for system level modeling.
6. Case Sensitivity: Unlike VHDL, Verilog is a case sensitive language.
7. Semantics: Both VHDL and Verilog have simulation-based semantics.
8. Compilation and Interpretation: VHDL is compiled, while Verilog is an interpretative language.
9. Simulation and Control Capabilities: Verilog defines a set of basic simulation control capabilities (system tasks) within language. As a result of these predefined system tasks and a lack of complex data types, Verilog users often run batch or command-line simulations and debug design problems by viewing waveforms from simulation results database. Unlike Verilog, VHDL does not define any simulation control and monitoring capabilities within language. These capabilities are tool-dependent. Due to the lack of language-defined simulation control command and because of user defined type capabilities, VHDL users usually rely on interactive GUI environments for debugging design problems.
10. Dynamic Memory Allocation: VHDL supports dynamic memory allocation (pointer types), while Verilog has no such feature.
11. Roots of Languages: VHDL is more readable and a strongly typed language with its roots from Ada. While, Verilog because of having its roots from C is more like C and is considered inherently sequential. Because of its affinity with C, Verilog is preferred by C programmers.
12. Lack of Constructs: Not all the constructs and operators are included in both languages. For example, unlike Verilog, VHDL does not have unary reduction operator. Similarly, unlike VHDL, Verilog does not have mod operator and concurrent procedure statement. So neither of these two hardware description languages is perfect.
13. Data types: Verilog has very simple data types, while VHDL allows users to create more complex data types.
14. Physical Types: VHDL supports physical types while Verilog does not support physical types.
15. Named Events: Verilog supports named events while VHDL does not support named events.
16. Enumerated Types: VHDLhas enumerated types (FSM modeling) while Verilog does not support this concept.
17. Associative/Sparse arrays: Verilog does not support the concept of Associative/sparse arrays,while VHDL partially supports this concept,which can be modeled in VHDL using access types.
18. Associative/Sparse arrays: There is no concept of class/inheritance in both Verilog and VHDL.
19. Data Packing: Both Verilog and VHDL do not support data packing.
20. Conidtional & Iterative Generation: Both Verilog (using if,if-else,case and for) and VHDL (using if and for) support conditional and iterative genration.
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